1. Field of the Invention
This invention is related to electronic systems and more particularly to communication of data in such systems.
2. Description of the Related Art
In computer systems such as personal computer systems, advances in input/output (I/O) bandwidth have generally lagged the advances in processing speed. That performance gap has resulted in systems being “I/O bound”, and as a result, the systems have been unable to fully exploit increased CPU processing speed.
I/O bandwidth has been determined in large part by the interconnect buses in the system. In conventional interconnect buses, a master device requests data from a slave device (or vice versa) and the bus remains tied up until the transaction completes. During the time the bus is waiting for either the sender or receiver of data to fulfill their part of the transaction, the bus is “busy”, thus blocking access to the bus by other masters. In order to improve bus utilization, more modern buses allow the master to send a transaction request to the slave and immediately release the bus. When the slave is ready for the transaction, the slave acquires the bus and completes the transaction with the master. Between the time that the master initiates the transaction, and the slave completes it, other transactions may be started and/or completed. This technique is known as “split transaction”. In this scheme, each transaction is “tagged” so that when the slave is ready to complete the transaction, the master knows the request to which it corresponds. It is also generally allowed that transactions be completed “out of order”, that is, in a different order than the order in which they were initiated.
Other solutions have been developed to address I/O bandwidth limitations. One such solution utilizes a point-to-point interconnect in which the bus is actually a fast serial link between nodes connected in a daisy-chain fashion (one device is connected to the other in succession and passes on anything that is not intended for it in both directions). One such bus is the HyperTransport™ as described in the HyperTransport™ I/O Link Specification, Revision 1.03 dated Oct. 10, 2001. Such buses have made advances in reducing or eliminating the bottleneck caused by I/O bandwidth limitations and have thus increased the potential gain available from additional processing speed as it becomes available.
Another traditional way of making more CPU processing power available in addition to increasing I/O bandwidth has been to off load tasks from the main processor onto a specialized co-processor. That has been done, e.g., in graphics processing in conventional personal computer systems. In such systems, graphics processing is performed by integrated circuit(s) that are separate from the CPU. The graphics processing circuits may be may be located on a separate graphics card. A specialized bus such as the Accelerated Graphics Processing (AGP) bus couples the graphics processing circuits to the rest of the system. As shown in FIG. 1, which illustrates an exemplary current personal computer system, the AGP bus 11 couples the north bridge integrated circuit 13 to graphics card 15. The north bridge 13 functions as the memory controller (among other roles) for memory 17. The graphics card 15 may include one or more graphics chips as well as memory.
It would be desirable to further simplify the transmission of data in computer systems to enhance system performance. Further, it would be desirable to enable the offloading of additional functions from the processor on other specialized coprocessor functions.